The present invention relates to semiconductor devices and a method of manufacturing the same, and especially relates to an improvement for solid state image sensors.
Solid state image sensors have been investigated for the use in different types of equipment such as video cameras. Interline CCD image sensors are well known image sensors which are commonly used for this type of application.
FIG. 1 shows a cross sectional view of a unit cell of this type of well known device. At the surface of a p-type Si (silicon) substrate 1, n-type region 2 is formed corresponding to a picture element. This region is a photodiode that performs photoelectric conversion of incident light form an image, and accumulates electric charges obtained. Adjacent to the n-type region 2, an n-type channel region 3 is formed as a buried channel of the vertical CCD (charge coupled device). The p.sup.+ -type region 4 is a channel stopper. In the vertical CCD region, with gate insulating films therebetween, double poly-Si films for transfer electrodes 5 and 6 are formed. Furthermore, onto this substrate, a light shield film 7 of Al that covers the CCD region is stacked, and a passivation film 8 of SiO.sub.2 is formed.
FIG. 2 shows the structure of an entire chip of the interline CCD image sensor. P.sub.11, P.sub.12, . . . , Pmn are the picture elements arranged in a matrix form, and 21 denotes a plurality of vertical CCD regions that are adjacent to the picture element lines. 22 shows a lateral CCD region that reads out the electric charges transferred to it by the vertical CCD regions 21. Each vertical CCD region 21 ordinarily comprises a four electrode cell CCD and is driven by a four phase clock producing pulse signals V.sub.1 through V.sub.4. The lateral CCD region 22 is a two electrode cell CCD and is driven by a two phase clock producing signals H.sub.1 and H.sub.2.
FIG. 3a through FIG. 3c show the transfer steps from the vertical CCD region to the lateral CCD region. In FIG. 3a, the electric charges 31 are positioned in a potential well beneath the transfer electrode that is formed before the end transfer electrode 33 of the vertical CCD region. These electric charges 31 are transferred to the storage transfer electrode 34 of the lateral CCD region when the end transfer electrode 33 opens as shown in FIG. 3b. After this step, the voltage of the clock pulse signals V.sub.3 and V.sub.4 becomes low, and then the transfer in the lateral CCD region begins. FIG. 3d shows the charges being transferred in the lateral CCD region. FIG. 3d also shows p-type impurities 36 introduced into the channel region.
However, one technical problem associated with this technique is the existence of residual charges 37 left behind in the transferring step of FIG. 3b in which charges are transferred toward the lateral CCD region. Such residual charges degrade the quality of the displayed image. For instance, these charges decrease the amount of electric charges transferred to the lateral CCD region. Although the residual charges diffuse into the substrate after this step, some are mixed with other signals that come in the next transferring step. In this case, if the next signal is a vacant signal corresponding to an unilluminated area, the signal would not be expressed exactly as a dark signal. Thus, all the picture elements along the vertical CCD line suffer the effect of the residual charges.